1. Field of the Invention
The present invention generally relates to semiconductor devices for integrated circuits, and more particularly to such semiconductor devices having a stress liner to enhance the performance of the devices.
2. Background Art
In general, semiconductor devices include integrated circuits having complementary pairs of P-channel transistors and N-channel transistors formed on a common semiconductor substrate. As is generally known in the art, CMOS technologies are typically used to fabricate IC (integrated circuit) chips for high density and high-performance applications due to, e.g., the high operation efficiency, high switching speed, and good scaling properties that are characteristic of CMOS devices. Technological innovations in semiconductor fabrication technologies are driving market demands for CMOS solutions for higher speed, higher integration density, and lower power applications. The downscaling of CMOS technologies to submicron design rules and beyond, however, poses technological challenges with respect to maintaining performance and reliability. For example, as device sizes are downscaled, CMOS transistors must be formed with, e.g., thinner gate electrodes, smaller channel lengths, and shallower drain/source extension diffusion regions. This downscaling generally results in transistors having higher channel resistance and higher junction/contact parasitic resistances, leading to degraded performance.
To mitigate the impact on device performance with downscaling, various state of the art CMOS fabrication techniques can be implemented to effectively reduce parasitic gate and junction resistances and increase channel conductivity. For example, DSL (dual stress liner) techniques can be incorporated in CMOS process flows as a means to enhance performance of highly-scaled CMOS devices. In general, DSL technologies are premised on findings that the application of compressive stress to the conduction channel of a P-type transistor can improve the carrier (holes) mobility within the channel, while the application of tensile stress to the conduction channel of an N-type transistor can improve the carrier (electrons) mobility within the channel. In this regard, various DSL techniques have been developed to form a compressive stress insulating liner over the gate structure of P-type transistors while forming tensile stress insulating liners over the gate structures of N-type transistor devices, so as to increase charge carrier mobility in the channels of the complementary transistors.
The deliberate introduction of strain into a silicon MOSFET channel has become an important route for improving device performance in CMOS technologies. Stress is typically coupled into the channel from the source/drain regions. However, as gate pitch is reduced in order to increase density, the size of the source/drain regions are shrinking rapidly, limiting the efficacy of such methods. Furthermore, in thin-body devices, the use of embedded source/drain elements to create stress is also not effective, due the difficulty of embedding stressed materials into a thin substrate that can effectively couple stress into the channel.
One alternative to using source/drain regions to create stress is to use stressed gate materials, which can transfer stress directly to the channel beneath it. However, the important role of the gate in both the processing used for device formation and the proper electrical functioning of the device results in extremely restrictive constraints on materials that can be considered for use in the gate, making the incorporation of significant stress difficult.